| 摘要 |
A semiconductor integrated circuit is disclosed, which comprises a tree structure of buffer circuit groups configured to have an enable-signal-controlled AND buffer circuit at least in a final stage, a latch circuit provided in a correspondence to the enable-signal-controlled AND buffer circuit and configured to receive an enable signal and clock signal and deliver an output to an input portion of a final stage buffer circuit, an enable-signal-controlled AND buffer circuit provided in a portion of an intermediate stage of the buffer circuit groups, and an OR circuit provided in a correspondence to the intermediate stage enable-signal-controlled AND buffer circuit and configured to take a logical sum of a plurality of enable signals for controlling the operations of a plurality of enable-signal-controlled AND buffer circuits more on a load circuit side and deliver a logical sum output to an input portion of the intermediate stage enable-signal-controlled AND buffer circuit.
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