发明名称 |
FREQUENCY MULTIPLIER |
摘要 |
<p>A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.</p> |
申请公布号 |
WO2004012335(A1) |
申请公布日期 |
2004.02.05 |
申请号 |
WO2003US22319 |
申请日期 |
2003.07.17 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
YEE, GIN;BOBBA, SUDHAKAR;OOI, LYNN;TRIVEDI, PRADEEP |
分类号 |
H03K5/00;(IPC1-7):H03K5/00;H03L7/16;H03K5/13 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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