发明名称 |
Semiconductor integrated circuit device and a method of manufacture thereof |
摘要 |
A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.
|
申请公布号 |
US2004021159(A1) |
申请公布日期 |
2004.02.05 |
申请号 |
US20030630695 |
申请日期 |
2003.07.31 |
申请人 |
HITACHI, LTD. |
发明人 |
MATSUOKA HIDEYUKI;YAMADA SATORU;ASANO ISAMU;NAGAI RYO;SEKIGUCHI TOMONORI;TAKEMURA RIICHIRO |
分类号 |
H01L21/8242;H01L27/02;H01L27/108;(IPC1-7):H01L27/108;H01L29/76;H01L29/94;H01L31/119 |
主分类号 |
H01L21/8242 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|