Vertical transistor memory cell comprises a substrate containing a trench, electrically insulated storage regions side walls of the trench, gates region arranged in the trench, and source/drain regions

摘要

Vertical transistor memory cell comprises a substrate containing a trench, a first electrically insulated storage region (201a, 201b; 202a, 202b) on a first sidewall of the trench, a second electrically insulated storage region (201c, 201d; 202c, 202d) on a second sidewall of the trench, a first gate region arranged in the trench on a the first storage region, a second gate region coupled with the first gate region on the second storage region, two first source/drain regions, and two second source/drain regions. One of the first source/drain regions is coupled with a lower end section of one of the storage regions and one of second source/drain regions is coupled with an upper end section of one of the storage regions. An Independent claim is also included for: (a) memory cell arrangement containing several vertical memory cells integrated on and/or in a substrate; (b) production of a vertical memory cell; and (c) process for operating a vertical transistor memory cell.