| 摘要 |
PROBLEM TO BE SOLVED: To provide a vertical synchronizing signal recovery circuit capable of generating a vertical synchronizing signal even from a signal whose total number of lines per field differs from that of a standard signal. SOLUTION: The vertical synchronizing signal recovery circuit includes: a line counter 4 for counting the total number of lines per filed; a field delay circuit 6 for latching a maximum count in a two-preceding field to a current field; a decode value calculation circuit 9 for estimating a series of pseudo counts continuing before and after the latched maximum count on the basis thereof to calculate decode values for a leading edge and a trailing edge of a vertical synchronizing signal 15 on the basis of a series of the estimated pseudo counts; and a vertical synchronizing signal generating circuit 14 that decodes counts corresponding to the decode values for the leading and trailing edges calculated by the decode value calculation circuit 9 by using a series of counts in the current field outputted from the line counter 4 to generate the vertical synchronizing signal 15. COPYRIGHT: (C)2004,JPO
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