| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock signal supply circuit less deteriorating performances under the worst conditions by suppressing the lowering of an operation speed due to dispersion in various types of conditions. <P>SOLUTION: A clock signal CLK is supplied to front stages FF21 and 22 of a logic circuit block 12, whose processing time is the longest, via delay buffers 41 and 42 using a capacitor as a delay element, while the clock signal CLK is supplied to the rear stages FF 23 and 24 via delay buffers 43 and 44 using a buffer by a transistor similar to the logic circuit block 12 as the delay element. When the processing time of the logic circuit block 12 increases by fluctuation of operation environment and the like to delay the output of processing result data, the timing of the clock signal to be supplied to the FF 23 and 24 is delayed by the same fluctuation of the operation environment. The FF 23 can thus receive the processing result of the logic circuit block 12 even for the fluctuation of the operation environment and the like. <P>COPYRIGHT: (C)2004,JPO</p> |
