| 摘要 |
PROBLEM TO BE SOLVED: To realize practical automatic layout design of the standard cell system by registering the cells with the input stage formed with a transfer gate in a library. SOLUTION: A cell library in which cells including the transfer gates at the input stage are registered and capacitance value of data signal input terminal of the transfer gate when it is ON and OFF is included as the attribute of cells, a net list, and the maximum allowable value of wiring length connected to the data signal input terminal of the transfer gate, are stored in a storage device. After the cells are aligned automatically (S1), the layout is corrected (S6, S7) and automatic wiring is performed when the through rate of the input waveform is equal to or larger than the predetermined value when the transfer gate is ON (S5), or when the hold time in the D flip-flop is equal to or larger than the predetermined value when the transfer gate is OFF. Moreover, when the wiring length has exceeded the allowable maximum value, the layout is corrected. COPYRIGHT: (C)2004,JPO
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