SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To efficiently perform a memory test by surely preventing output of data errors caused by coupling noise or the like. SOLUTION: A data control circuit 14 is provided with a NAND circuit ND6 and a circuit DD for preventing data inversion comprising an inverter Iv2. This circuit DD for preventing data inversion takes in data compression signals TDATA1-TDATA4 only in a period in which a main amplifier data output control signal MAEQiR is outputted at the time of on-chip compare-test, and prevents output errors of data inversion caused by coupling noise or the like. COPYRIGHT: (C)2004,JPO