Integrated memory with registers for storing data patterns for normal and test operation has enhanced registers for internal test pattern data

摘要

An integrated memory comprises a connection (10) for command signals (CS) in normal and test operation, a connection (20) for a different signal (CKE), registers (YA-YB) storing test data patterns and a register decoding unit (REGDEC) to choose the register. Inputs to this (21,22) are connected with the command and signal connections.