发明名称 CACHE MEMORY DEVICE AND BIT ERROR DETECTING METHOD FOR REFERENCE HISTORY
摘要 <P>PROBLEM TO BE SOLVED: To detect a bit error in a reference history without adding redundancy bit to the reference history in a cache memory device of Nway set associative system. <P>SOLUTION: This cache memory device of N way set associative system (N is an integer of 2 or more.) is provided with a way detecting part detecting a specific-strength-way based on the reference history, which a bit showing a win or lose relation between the ways and updated so as to show the specific-strength-way, and an error detecting part detecting the bit error in the reference history when the specific-strength-way is not detected by the way detecting part. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004038299(A) 申请公布日期 2004.02.05
申请号 JP20020191018 申请日期 2002.06.28
申请人 FUJITSU LTD 发明人 YOSHIZAWA SHUICHI;UKAI MASAKI
分类号 G06F11/07;G06F12/08;G06F12/12 主分类号 G06F11/07
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