发明名称 POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE
摘要 In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) (140) through both voltage and frequency adjustment of clock signal received from a clock generator (120). The GMCH (140) comprises a graphics core (200) and a circuit (235) to alter operational behavior, such as the frequency of a render clock signal (270) supplied to the graphics core (200). The circuit (235) is adapted to monitor idleness of the graphics core (200) and reduce a frequency level of the render clock (270) signal if the idleness exceeds a determined percentage of time.
申请公布号 WO03096170(A3) 申请公布日期 2004.02.05
申请号 WO2003US10428 申请日期 2003.04.02
申请人 INTEL CORPORATION 发明人 CUI, YING;SAMSON, ERIC;BERKOVITS, ARIEL;NAVALE, ADITYA;WYATT, DAVID;CLINE, LESLIE;TSANG, JOSEPH;BLAKE, MARK;POISNER, DAVID;STEVENS, WILLIAM, JR.;SAR-DESSAI, VIJAY
分类号 G06F1/04;G06F1/32 主分类号 G06F1/04
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