| 摘要 |
A method and system of monitoring code as it is executed by a target processor is provided for debugging, etc. Standardized software code function preamble and postamble instructions are dynamically replaced with instructions that will generate a predetermined exception. This exception is of a type included in the standard instruction set of the target processor, such as a misalignment exception. The exception generates a branch to a conventional exception vector table. An exception routine is inserted into the vector table, and includes instruction(s) to disable the data and/or address caches. Subsequent instructions in the vector table execute the replaced preamble instruction and, with or without re-enabling the cache, branch back to the address of the program code immediately following the faulted preamble address. Instructions of the function executed while cache is disabled are executed on the bus where they are visible, as opposed to within cache. The function continues to execute until the substitute postamble instruction generates a second misalignment exception. This second exception will branch the program back to the exception table which executes as discussed above and then re-enables the cache. The vector table branches back to an address subsequent to the faulted postamble and then to the calling function to enable the remainder of the program to run in a cache-enabled fashion.
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