Semiconductor memory device and associated data read method

摘要

The inventive semiconductor memory device includes a data output buffer adapted to receive input data responsive to an on time control signal and adapted to buffer the input data responsive to a latch clock signal. A first clock signal generating means is adapted to generate a first clock signal responsive to a reference signal. A second clock signal generating means is adapted to generate a second clock signal responsive to the first clock signal and a mode signal. A latency signal generating means is adapted to generate a latency signal responsive to the mode signal. A latch clock generating means is adapted to generate the latch clock signal responsive to the second clock signal and the mode signal. And an on time control signal generating means is adapted to generate the on time control signal responsive to the second clock signal and the latency signal.