| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of input/output buffer cells in a block to be inserted without increasing any delay analysis error. SOLUTION: A signal delay time from a flip flop in another block to each input terminal of a block being focused is estimated, and logical cells connected to the plurality of input terminals of the block being focused are extracted from the netlist of circuits in the block being focused, and a distance between the plurality of input terminals of the block being focused connected to each of the extracted logical cells is calculated, and when the distance is not less than a distance 200μm applied as design constraint, a buffer cell is inserted into the node of any input terminal other than the input terminal whose signal delay time is the maximum value among the plurality of input terminals of the block being focused connected to each of the logical cells, and the logical cell is arranged adjacently to the input terminal whose signal delay time is the maximum value while any buffer cell is not inserted into the node of the input terminal whose signal delay time is the maximum value. COPYRIGHT: (C)2004,JPO
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