发明名称 Wafer-level test of integrated circuits
摘要 A plurality of integrated circuits are inspected for their characteristics, after applying uniform stresses to the integrated circuits from common interconnections. Circuit forming means form common interconnections which are connectable in common to like electrode pads of the integrated circuits on the circuit substrate. By stress applying means, uniform stresses are applied from the common interconnections to the integrated circuits while the electrode pads of the integrated circuits are being connected to the common interconnections corresponding thereto. By interconnection disconnecting means, the electrode pads are disconnected from the common interconnections after the uniform stresses have been applied to the integrated circuits. By circuit inspecting means, the integrated circuits which have been disconnected from the common interconnections are individually inspected to determine whether the integrated circuits are acceptable or not, using the electrode pads. <IMAGE>
申请公布号 EP1328016(A3) 申请公布日期 2004.02.04
申请号 EP20030000272 申请日期 2003.01.08
申请人 NEC ELECTRONICS CORPORATION 发明人 KUMAMOTO, KENYA
分类号 G01R31/30;G01R31/28;H01L21/66;H01L23/544 主分类号 G01R31/30
代理机构 代理人
主权项
地址