发明名称 |
High-level synthesis method, high-level synthesis apparatus, method for producing logic circuit using the high-level synthesis method for logic circuit design, and recording medium |
摘要 |
A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.
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申请公布号 |
US6687894(B2) |
申请公布日期 |
2004.02.03 |
申请号 |
US20010984897 |
申请日期 |
2001.10.31 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
OHNISHI MITSUHISA;TANAKA SHINICHI |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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