| 摘要 |
To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks (9) that each memory block (9) has a corresponding data bus and a group of sense amplifiers (1) connected to this data bus (2) associated with it. In this way it is possible for the bus-line capacitance (CB), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector (6).
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