发明名称 Logic analyzer testing method and configuration and interface assembly for use therewith
摘要 The logic analyzer interface assembly connects to a unit under test (UUT). The interface assembly includes an interface board having interface contact points matching the pattern of the UUT contact points. The interface board is mounted to a transfer interface including a probe plate and multiple spring loaded probes extending through the probe plate. The probes contact the UUT contact points at one end and the interface contact points at the other end. When assembled, the UUT and interface assembly form a sandwiched testing assembly that can be inserted into a chassis to aid in approaching an "at speed" observation opportunity.
申请公布号 US6685498(B1) 申请公布日期 2004.02.03
申请号 US20020259206 申请日期 2002.09.27
申请人 JONES RONALD;SCHEELER SCOTT;GRAHAM RICHARD 发明人 JONES RONALD;SCHEELER SCOTT;GRAHAM RICHARD
分类号 H01R11/18;(IPC1-7):H01R11/18 主分类号 H01R11/18
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