发明名称 Method and system for exposed die molding for integrated circuit packaging
摘要 A method for exposed die molding for integrated circuit packaging is provided that includes providing a mold comprising an upper mold with a flexible material, a lower mold, and a floating plunger. A substrate of an integrated circuit structure is clamped between the upper mold and the lower mold. An integrated circuit die of the integrated circuit structure is clamped between the floating plunger and the upper mold through the flexible material.
申请公布号 US6686227(B2) 申请公布日期 2004.02.03
申请号 US20020062218 申请日期 2002.02.01
申请人 STMICROELECTRONICS, INC. 发明人 ZHOU TIAO;HUNDT MICHAEL J.
分类号 H01L21/56;H01L23/31;(IPC1-7):H01L21/44;H01L21/48;H01L21/50 主分类号 H01L21/56
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