| 摘要 |
PURPOSE: To shorten the time of access without increasing power consumption in a semiconductor memory which has a dynamic memory cell. CONSTITUTION: An operation control circuit sets a deactivation timing of a sense amplifier, which has been activated in accordance with a reading request, a writing request, and a refresh request, in correspondence to a timing with which the maximum amount of signals that can be outputted from the sense amplifier operating in response to the refresh request are transmitted to a memory cell. It is possible to shorten the time of access by matching an activation period of time of the sense amplifier to the refresh operation. In a refresh control circuit, the refresh requests are consecutively generated for a specified number of times and a generating cycle of the refresh request signal is lengthened after refreshing all the memory cells. When the refresh request is consecutively generated, a frequency of reflesh is lowered and power consumption can be reduced. As a result, it is possible to shorten the time of access without increasing the power consumption when it is in a standby mode.
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