HIGH-VOLTAGE VDMOS TRANSISTOR AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A high-voltage VDMOS(Vertical Double diffused MOS) transistor and a fabricating method thereof are provided to reduce Rdson(ON resistance between a source and a drain terminal) by burying a conductive material into an epitaxial layer to form a plug type drain. CONSTITUTION: The second conductive type high-density buried layer(15) is formed on the first conductive type semiconductor substrate(10). An isolation trench is formed by etching the second conductive type high density buried layer(15) and the first conductive type semiconductor substrate(10). An isolation layer(25) is formed by filling an insulating layer. The second conductive type low-density epitaxial layer(30) is grown on the buried layer and the isolation layer. A trench is formed by etching the isolation layer. An insulating layer spacer(45a) is formed at a sidewall of the trench adjacent to the isolation layer(25). The second conductive type drain(60) is formed by filling the conductive material into the trench. A gate(130) and a source are formed on the resultant.