| 摘要 |
PURPOSE: A synchronous compensation circuit and a controlling method thereof are provided to generate separately a clock of an input signal and a clock of a signal for signal process by using a dual port FIFO. CONSTITUTION: A synchronous compensation circuit includes a backplane(10), a signal processor(40), and a memory(50). The backplane(10) is used for outputting data through a data bus. The signal processor(40) is used for outputting a read signal. The memory(50) is used for increasing write addresses and storing data according to a write signal in a data input process or increasing read addresses and outputting the stored data according to the read signal in a data output process. The memory(50) is formed with an address counter(50a) for increasing the addresses of the input data and a dual port FIFO(50b) for outputting the input data.
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