| 摘要 |
PURPOSE: A structure of a gate of a flash memory cell, a forming method thereof, and a method for forming a dielectric layer are provided to maximize an area of an electrode and satisfy a required coupling ratio by forming a porous portion on an upper surface of a gate. CONSTITUTION: A structure of a gate of a flash memory cell includes a tunnel oxide layer(104), the first floating gate(106), the first dielectric layer(108), the second floating gate, the second dielectric layer, and a control gate. The tunnel oxide layer(104) is formed on a predetermined region of a semiconductor substrate(100). The first floating gate(106) is formed on the tunnel oxide layer(104). The first dielectric layer(108) is formed on the first floating gate. The second floating gate is formed on the first dielectric layer(108). The second dielectric layer is formed on the second floating gate. The control gate is formed on the second dielectric layer.
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