发明名称 VIDEO SIGNAL PROCESSING APPARATUS, VIDEO SIGNAL PROCESSING METHOD, AND PROGRAM AND RECORDING MEDIUM FOR REALIZING THE METHOD
摘要 PROBLEM TO BE SOLVED: To adjust the phase of a transfer clock of digital graphic data. SOLUTION: An image processing circuit 300 comprises a phase adjusting circuit 320 for generating a plurality of sampled blocks obtained by delaying by a predetermined time a synchronous signal for video data in succession; and a judgement circuit 330 for calculating coordinates where a difference between video data of adjacent picture elements is maximum, and extracting a group of two or more of sampling clocks wherein calculated coordinate values are the same, and delay times of the sampling clocks are closest to each other, and further determining a delay time at the center of the sampling clock involved in the extracted group of the sampled clocks as an optimum delay time. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004032148(A) 申请公布日期 2004.01.29
申请号 JP20020182534 申请日期 2002.06.24
申请人 KANEBO LTD 发明人 YASUOKA TAKASHI;MIYAKE TOSHIHIRO
分类号 H04N5/12;G09G5/12;H04N5/14;(IPC1-7):H04N5/12 主分类号 H04N5/12
代理机构 代理人
主权项
地址