发明名称 INTERCONNECTION MECHANISM OF VIRTUAL I/O
摘要 PROBLEM TO BE SOLVED: To enable a transaction the address of which is specified in a failed component to request an alternate component. SOLUTION: This interconnection mechanism of virtual I/O comprises an address decode block having a multiplexer 172 which generates an address 173 in relation to a processing unit related transaction by multiplexing input, a range register decoder 174 which receives the address and provides a destination address 175 of a module for receiving the transaction in relation to the address and a reroute module ID block 176 which receives the destination address and a reroute module ID block having an original module ID 182 which provides addresses of one or more original modules in a computer system and a remapping module ID 183 which provides a logical destination module ID of an alternate module in the computer system. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004030578(A) 申请公布日期 2004.01.29
申请号 JP20030063486 申请日期 2003.03.10
申请人 HEWLETT PACKARD CO <HP> 发明人 SHARMA DEBENDRA DAS;GUPTA ASHISH
分类号 G06F13/14;G06F3/00;G06F11/00;G06F11/20;G06F13/00;(IPC1-7):G06F13/14 主分类号 G06F13/14
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