In a BIST (built-in-self-test) system (300) for testing flash memory cells (304) fabricated on a semiconductor substrate (302), a BIST (built-in-self-test) interface (312), a front-end state machine (314), and a back-end state machine (316) are fabricated on the semiconductor substrate (302). The BIST interface (312) inputs test mode data from an external test system (318), and the front-end state machine (314) decodes the test mode data to determine an order for performing at least one desired test mode. The back-end state machine (316) performs the at least one desired test mode on the flash memory cells (304) according to the order for on-chip testing of the flash memory cells (304).
