发明名称 MODEL-BASED LOGIC DESIGN
摘要 A rechnique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
申请公布号 WO03021495(A3) 申请公布日期 2004.01.29
申请号 WO2002US27005 申请日期 2002.08.23
申请人 INTEL CORPORATION (A DELAWARE CORPORATION) 发明人 WHEELER, WILLIAM;ADILETTA, MATTHEW;FENNELL, TIMOTHY;CLARK, CHRISTOPHER
分类号 G06F17/50 主分类号 G06F17/50
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