Method and apparatus to facilitate detecting a slow node in a circuit layout

摘要

One embodiment of the present invention provides a system that facilitates detecting one or more slow nodes in an integrated circuit layout. During operation, the system receives an integrated circuit layout. Next, the system inserts repeaters into signal lines of the integrated circuit layout to define a set of nets. The system then produces a resistance/capacitance (R/C) model for each net and obtains a timing model for each driver and receiver in the integrated circuit layout. This timing model specifies a non-linear circuit model for each driver and a non-linear circuit model for each receiver in the layout. The system then performs a circuit simulation using the timing model for each driver and receiver and the R/C model for each net. The system uses results of this circuit simulation to identify one or more slow nodes in the integrated circuit layout.