| 摘要 |
A multiple processor integrated circuit includes a plurality of processing units, cache memory, a memory controller, an internal bus, a packet manager, a node controller, configurable packet-based interfaces, and a switching module. The internal bus couples the plurality of processing units, the cache memory, the memory controller, the packet manager, and the node controller together. The switching module couples the configurable packet-based interfaces with the packet manager and node controller. Each of the packet-based interfaces may be configured to provide a tunnel function, a bridge function, and/or a tunnel-bridge hybrid function. In the tunnel-bridge hybrid mode, the packet-based interfaces enable the multiple processor integrated circuit to provide peer-to-peer communication with other multiple processor integrated circuits in a processing system that includes a plurality of multiple processor ICs.
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