| 摘要 |
PROBLEM TO BE SOLVED: To shorten a time necessary for instruction processing by suppressing an occurrence of cross bypass use while realizing efficient processing using parallel processing. SOLUTION: An instruction processor is provided with an instruction buffer 2 for storing instructions, a plurality of decoders 4 that can parallelly decode a plurality of instructions issued simultaneously from the instruction buffer 2, a plurality of computing elements 6 for processing the instructions decoded by the decoders 4, a limiting means 22 for the number of instruction issued that limits the number of instructions issued from the instruction buffer 2 to the plurality of decoders 4 so as to bias the frequency of processing the instruction to one computing element among the plurality of computing elements 6 while using all of the computing elements 6 to process the instructions. COPYRIGHT: (C)2004,JPO
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