SIGNAL PROCESSING DEVICE, NON-INTEGER DIVIDER, AND FRACTIONAL N-PLL SYNTHESIZER USING THE SAME

摘要

An adder (2) and a delay device (4) constitute a 20-bit input accumulator, which is connected to a signal input terminal (1). An adder (8) and a delay device (10) constitute a 9-bit input accumulator. The most significant 8 bits of output of the adder (2) are input to the most significant 8 bits of the 9-bit input accumulator. The least significant bit input of the 9-bit input accumulator is connected to the output of a 3-input NAND gate (30). An adder (13) and a delay device (15) constitute a 6-bit input accumulator, to which most significant 6 bits of the output of the adder (8) are input. An adder (18) and a delay device (20) constitute a 4-bit input accumulator, to which the most significant 4 bits of the output of the adder (13) are input. The 3-input NAND gate is supplied with the least significant 3 bits of the output of the delay device (20).