DIGITAL PHASE LOCKED LOOP CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a digital phase locked loop circuit which has a wide capture range and stably locks synchronization at a high speed. SOLUTION: The digital phase locked loop circuit generates a recovery clock to read digital data recorded on a recording medium with a prescribed data format to obtain a recovered digital signal and synchronizes a phase of the recovered clock with a phase of a clock component of the recovered digital signal on the basis of phase difference error information obtained from prediction of a zero cross point in a random signal area of the digital data and another item of phase error information detected from a random signal in the digital data. COPYRIGHT: (C)2004,JPO