| 摘要 |
In an FM multiplex decoder circuit of this invention, when the cycle interval of detection signal of continuous "1" or "0" elongates and therefore erroneous sampling clock occurs, the shift clock is forced into stopping. Therefore, erroneous extra data is not sent to the shift register, thereby data that detection signal is normally decoded can be output from the shift register. Also, even when the cycle interval of detection signal of continuous "1" or "0" shortens to elongate the sampling clock cycle and therefore data to be taken by the latch circuit decreases, in a shift clock period newly generated, inverted latch signal can be taken by the shift register. Thus, the shift register can take data lost to latch signal. Therefore, data that detection signal is normally decoded can be output from the shift register. <IMAGE> |
