| 摘要 |
PURPOSE: A method for forming a metal line of a semiconductor device is provided to be capable of reducing the CD(Critical Dimension) bias of an isolation pattern. CONSTITUTION: After the first metal material layer is formed at the upper portion of a semiconductor substrate(21), a compact pattern(23a) is formed by selectively patterning the first metal material layer. An interlayer dielectric(27b) is formed on the entire surface of the resultant structure. A trench is formed at the predetermined portion of the resultant structure for defining an isolation pattern region by selectively patterning the interlayer dielectric. After the second metal material layer is formed at the upper portion of the resultant structure, an isolation pattern(33) is formed at the inner portion of the trench by carrying out a planarization process at the second metal material layer and the interlayer dielectric.
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