发明名称 |
AN APPARATUS FOR CONTROLLING ACCESS IN A DATA PROCESSOR |
摘要 |
A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability. |
申请公布号 |
EP1384158(A2) |
申请公布日期 |
2004.01.28 |
申请号 |
EP20020721883 |
申请日期 |
2002.03.04 |
申请人 |
ATSANA SEMICONDUCTOR CORP. |
发明人 |
STEWART, MALCOLM;GIERNALCZYK, ERIC;BERIAULT, RICHARD |
分类号 |
G06F3/00;G06F7/575;G06F9/302;G06F13/16;G06F15/173;G06F15/80;(IPC1-7):G06F15/173 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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