| 摘要 |
An integrated circuit device that includes a clock synchronization circuit. The clock synchronization circuit receives an external clock signal and generates an internal clock signal from the external clock signal using a feedback loop. The internal clock signal is adjusted based on feedback provided via the feedback loop. In addition, the integrated circuit device includes an output circuit. The output circuit includes an output driver to output at least two bits of data in succession during a clock cycle of the external clock signal. The data is output synchronously with respect to the internal clock signal.
|
