| 摘要 |
A method for fabricating a gate of a flash memory is described. A tunneling oxide layer, a first polysilicon layer and a silicon nitride layer are sequentially formed on a substrate. A photo-resist layer is formed on the silicon nitride layer and then the photo-resist layer, the silicon nitride layer, the polysilicon layer, the tunneling oxide layer and the substrate are patterned to form a plurality of trenches in the substrate. An active area defined by every two trenches is simultaneously formed. The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the top of the silicon nitride layer. The top portion of the shallow trench isolation structures is removed to expose the sidewall of the silicon nitride layer and the top portion of the sidewall of the first polysilicon layer. Part of the silicon nitride layer is removed by wet etching. Then, a second polysilicon layer is formed on the active area and the shallow trench isolation structures. The second polysilicon layer is etched anisotropically to further expose the top face of the shallow trench isolation structures to form a floating gate. The remaining silicon nitride layer is removed. A conformal dielectric layer is formed over the substrate. A third polysilicon layer is formed on the dielectric layer as a control gate.
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