| 摘要 |
A system and method for decoding the length of a macro instruction is described. In one embodiment, the system comprises an opcode-plus-immediate logic unit to generate a first length value, the first length value comprising a length of an opcode plus a length of intermediate data. A memory-length logic unit generates a second length value, the second length value comprising a potential length of a memory displacement, the opcode-plus-immediate logic unit and memory-length logic unit operating in parallel. In addition, the system comprises a length-summation logic unit to sum the first length value and the second length value if the second length value is present.
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