| 摘要 |
PURPOSE: A system clock duplex device is provided to rapidly synchronize the activation board and the waiting board during the duplex supply of the system clock. CONSTITUTION: A system clock duplex device includes a pair of phase lock loop(PLL)(210a,210b), a pair of PLDs(220a,220b), a pair of first delays(230a,230b), a pair of second delays(235a,235b) and a pair of pass selection units(250a,250b) and a pair of second pass selection units(260a,260b). The pair of phase lock loop(PLL)(210a,210b) remove the phase noise of the reference clock and makes the reference clock same as the reference frequency to compare the phase of it. The pair of PLDs(220a,220b) compare the phase of the system clock with the phase of the clock inputted from the other board. The pair of second delays(235a,235b) synchronize the primary clock and the secondary clock transmitted from the global positioning system(GPS) with the activation clock by giving different phases to the primary clock and the secondary clock, respectively. The pair of pass selection units(250a,250b) select so as to supply the system clock to the side which is primarily capable of synchronizing among the primary clock and the secondary clock. And, the pair of second pass selection units(260a,260b) supply the system clock to the device board in response to the control signal transmitted from the pair of PLDs(220a,220b).
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