| 摘要 |
PURPOSE: A method for forming a gate of a dual gate logic element is provided to be capable of preventing the height difference of an N-type gate and a P-type gate. CONSTITUTION: A gate oxide layer(10) and a polysilicon layer(20) are sequentially formed on a semiconductor substrate. An additional blocking layer(30) is formed on the polysilicon layer(20) to expose a P-type gate forming region. A compensation silicon layer(50) is formed on the exposed p-type gate formation region by SEG(Selective Epitaxial Growth) or CVD. Then, an N-type and P-type gate having the same height are formed.
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