SIGMA DELTA MODULATOR

摘要

A sigma delta modulator having an integrator with a first input for coupling to an analog signal and a second input for coupling to a reference voltage. A comparator has a first input coupled to an output of the integrator and a second input coupled to the reference voltage. The comparator produces signal having a logic state in accordance with the relative magnitude of signals at the first and second inputs thereof. The logic state is latched at the comparator output during latching transitions of latching pulses. A one-bit quantizer stores the logic state of at the comparator output at sampling transitions of clock pulses fed to the quantizer. The clock pulses and the latching pulses are synchronized one with the other. Each one of the latching transitions occurs prior to a corresponding one of the sampling transitions.