| 摘要 |
A charge-pump phase-locked loop (CP-PLL) circuit with charge calibration. The CP-PLL circuit keeps the phase of an output clock signal constant in a "locked" condition, and includes a charge-pump circuit and a calibration circuit. The charge-pump circuit provides a charge-pump output current. The charge-pump circuit also includes a transistor configured to fine tune the charge-pump output current based on a calibrate voltage signal to eliminate a net charge delivered from the charge-pump output current. The calibration circuit senses the net charge and generates the calibrate voltage signal having a value in proportion to an amount of the net charge. Under control of the calibrate voltage signal, the charge-pump circuit cooperating with the transistor regulates the net charge to become exactly zero, thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.
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