发明名称 Layout quality analyzer
摘要 In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
申请公布号 US2004015805(A1) 申请公布日期 2004.01.22
申请号 US20020200365 申请日期 2002.07.22
申请人 KIDD DAVID A.;DIAS NATHAN D.;PAGE MATTHEW J. 发明人 KIDD DAVID A.;DIAS NATHAN D.;PAGE MATTHEW J.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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