| 摘要 |
PROBLEM TO BE SOLVED: To solve the problems that insertion of a latch in a wire path suffers from poor performance, and building a latch into an ordinary buffer adds significant delay. SOLUTION: A latch circuit for receiving a data signal and a clock signal and for providing an output signal comprises a complement reset buffer including a first pulse generator 120 and a second pulse generator 140, a state element 1120 coupled to receive the data signal and the clock signal and configured to produce a state output responsive to the clock signal, gate circuits 1150 and 1152 configured to disable the first pulse generator and the second pulse generator responsive to the clock signal, and an output stage 115 coupled to receive the state output from the state element and configured to provide the output signal. COPYRIGHT: (C)2004,JPO
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