发明名称 |
Layout design process and system for providing bypass capacitance and compliant density in an integrated circuit |
摘要 |
An IC layout design process and system involves placing an adjustable capacitor cell having a plurality of sub-cells, each with a polysilicon shape disposed over a corresponding active area shape. The polysilicon shapes are electrically coupled to a first power rail and the active area shapes are electrically coupled to a second power rail. The sub-cells of the adjustable capacitor cell are operable to be modified to satisfy a density measurement associated with the IC's fabrication flow.
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申请公布号 |
US2004015802(A1) |
申请公布日期 |
2004.01.22 |
申请号 |
US20020197346 |
申请日期 |
2002.07.17 |
申请人 |
CLOUDMAN JOHN ANDREW FRANCIS;LACHMAN JONATHAN;MICHELL NICHOLAS |
发明人 |
CLOUDMAN JOHN ANDREW FRANCIS;LACHMAN JONATHAN;MICHELL NICHOLAS |
分类号 |
G06F9/45;G06F17/50;H01L21/822;H01L27/02;H01L27/08;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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