发明名称 |
Integrated magnetoresistive semiconductor memory configuration |
摘要 |
An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.
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申请公布号 |
US2004013022(A1) |
申请公布日期 |
2004.01.22 |
申请号 |
US20030439738 |
申请日期 |
2003.05.16 |
申请人 |
BOEHM THOMAS;ROEHR THOMAS;HOENIGSCHMID HEINZ |
发明人 |
BOEHM THOMAS;ROEHR THOMAS;HOENIGSCHMID HEINZ |
分类号 |
G11C11/15;G11C11/16;H01L21/8246;H01L27/105;H01L27/22;H01L43/08;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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