| 摘要 |
<P>PROBLEM TO BE SOLVED: To enable high-speed phase pull-in and high-accuracy skew adjustment. <P>SOLUTION: This device relates to a PLL (phase-locked loop) circuit in which one of multi-phase pulse signals CK0DIV-CKNDIV which are generated by an output of a control oscillator 5 is phase-compared with an input signal by a phase comparator 1 as a channel clock, and the oscillation frequency of the oscillator 5 is controlled on the basis of the phase difference signal. The PLL circuit is provided with a frequency fixing circuit 9 for outputting an actuating signal PCSTART of the control when an input signal has the frequency almost the same as the frequency of the channel clock, and the input signal is within a capture range of the phase comparator; and a selecting circuit 7 for selecting, as the channel clock, a multi-phase signal having a phase which is the most similar to that of the time point of generation of the input signal after generating the actuating signal. After selecting the multi-phase pulse signal as the channel clock, the circuit 7 judges whether the input signal delays or advances compared to the channel clock, generates an advance signal or a delay signal according to the delay or advance, and controls a skew adjusting circuit 8 on the basis of the advance signal or the delay signal. <P>COPYRIGHT: (C)2004,JPO |
