A clock generator for an integrated circuit with a high-speed serial interface

摘要

The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fibre Channel, or Serial Attached SCSI (SAS), among others. The present invention also includes a method of generating a timing reference signal in a IC that includes generating a high-frequency signal with the high-speed timing reference generator of a high-speed serial interface, then using a initial divider to generate a mid-frequency timing reference signal from the high-frequency timing reference signal, and then using a final divider to generate a final timing reference signal from the mid-frequency timing reference signal. In the present method, timing reference signals generated from a phase locked loop (PLL) macrocell are not required.