发明名称 Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt
摘要 When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
申请公布号 US6681280(B1) 申请公布日期 2004.01.20
申请号 US20000678732 申请日期 2000.10.04
申请人 FUJITSU LIMITED 发明人 MIYAKE HIDEO;SUGA ATSUHIRO;NAKAMURA YASUKI
分类号 G06F9/46;G06F9/48;G06F13/24;(IPC1-7):G06F13/24 主分类号 G06F9/46
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