发明名称 MULTIPLYING-AND-DIVIDING UNIT
摘要 FIELD: automatic control and computer engineering. SUBSTANCE: proposed unit that can be used for processing signals in code and pulse-width forms and for yielding results in code and pulse-frequency forms has register, reversing counter, two AND gates, two binary multipliers, second reversing counter, two units for evaluating more significant setting bit, and NOR gate. EFFECT: enhanced speed of unit. 1 cl, 3 dwg
申请公布号 RU2222042(C2) 申请公布日期 2004.01.20
申请号 RU20020105225 申请日期 2002.02.26
申请人 发明人 BURENEVA O.I.;SAF'JANNIKOV N.M.
分类号 G06F7/62 主分类号 G06F7/62
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